1. Field
The present invention relates to a semiconductor memory including a bit line and a word line connected to a memory cell.
2. Description of the Related Art
In a semiconductor memory such as a DRAM, a memory cell is connected to one of a pair of complementary bit lines via a transfer gate which operates according to the voltage of a word line. In a read operation, data held in the memory cell is outputted to one of the bit lines. Before the read operation, the other of the bit lines is set to a precharge voltage. Then, a voltage difference between the bit line pair is amplified by a sense amplifier and outputted as read data. Generally, while the DRAM stands by, the bit line is set to the precharge voltage, and the word line is set to a ground voltage or a negative voltage.
For example, when the word line and the bit line are electrically shorted and a failure occurs, the failure word line is replaced with a redundancy word line. Alternatively, the failure bit line pair is replaced with a redundancy bit line pair. However, the short between the word line and the bit line physically exists even after the failure is relieved. Therefore, even after the failure is relieved, a leak current flows from a precharge voltage line to a ground line or a negative voltage line via a shorted portion. A DRAM with a large leak current is eliminated as a bad chip.
A method of placing a resistor element between the precharge voltage line and the bit line to reduce a standby current failure caused by the short failure between the word line and the bit line is proposed (for example, Japanese Unexamined Patent Application publication No. Hei 8-263983). Moreover, a method of connecting the bit line to the precharge voltage line only during a given period before the word line is activated and setting the bit line to a floating state during the other period (standby period) is proposed (for example, Japanese Unexamined Patent Application Publication No. Hei 4-47588, Japanese Unexamined Patent Application Publication No. Hei 6-52681).
Further, generally, to prevent a forward current (substrate current) of a pn junction from flowing between a substrate and a source/drain of a transistor, the low level voltages of the source and drain of an nMOS transistor are set to a substrate voltage or higher (for example, Japanese Unexamined Patent Application Publication No. 2005-135461).
In the common DRAM, the substrate voltage of the nMOS transistor connected to the bit line is set to the ground voltage or the negative voltage. The voltage of the bit line changes to an internal power supply voltage or the ground voltage during an access operation and is set to the precharge voltage (half the value of the internal power supply voltage) during the standby period. Hence, the substrate current does not flow to the nMOS transistor connected to the bit line.
However, if a short failure occurs between the word line and the bit line in a semiconductor memory in which the bit line is set to the floating state during the standby period, the voltage of the bit line gradually charges to a low level voltage of the word line during the standby period. If the low level voltage of the word line is lower than the substrate voltage of the nMOS transistor connected to the bit line, the substrate current flows to the nMOS transistor. As a result, even in the semiconductor memory with a specification designed to set the bit line to the floating state during the standby period, a leak current failure occurs.